A C-like hardware description language adding HLS-like automatic pipelining

PipelineC

A C-like(1) hardware description language (HDL)(2) adding HLS(high level synthesis)-like automatic pipelining(3) as a language construct/compiler feature.

1. Not actually regular C. But mostly compileable by gcc for doing basic functional verification/’simulation’.
   This is for convenience as a familiar bare minimum language prototype, not as an ideal end goal. Reach out to help develop something more complex together!
2. Can reasonably replace Verilog/VHDL. Compiler produces synthesizable and human readable+debuggable VHDL. Hooks exist for inserting raw VHDL / existing IP / black boxes.
3. If a computation can be written as a pure function without side effects (i.e. no global/static variables) then it will be autopipelined.
   Conceptually similar to technologies like Intel’s variable latency Hyper-Pipelining
   and Xilinx’s retiming options.
   Sharing some of the compiler driven pipelining design goals of

    

    

    

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